In the memory manufacturing industry, memory cells on a memory device (such as a semiconductor memory) are tested after fabrication of the device.
Conventionally, memory devices have a main memory comprising a large number of memory cells, and also a small number of redundant memory cell structures which can be substituted for any defective memory cells in the main memory. During the test process, the location of defective cells in the main memory is identified in order that through a process of redundancy allocation, these redundant memory cell structures can be configured to replace the defective cells in the main memory.
Other applications of memory test include the examination of electrical or functional parameters of the memory for engineering or quality control purposes, or verification of the operation of the memory.
Test systems used for testing memory devices must be able to test each new generation of memory devices at the maximum speed of the new device. The test systems must also be able to record a large number of locations. These factors combine to create a requirement for a large and expensive memory (called the fault capture memory or error catch RAM) in test systems because the fault capture memory must be the same size and operate at the same speed as the memory device under test. Some systems have used FIFOs to reduce the amount of RAM, but this still requires a large memory in the control system to which the tester is connected to process or view the defect data.
When the latest generation of memory devices is manufactured, there must be a test system available which is capable of testing these new memory devices; however, these test systems must be fabricated using the previous generation of memory devices. To enable the test systems to operate effectively, the requirement for storing the locations of defective cells is met by emulating the fault generating capacity of the new memory devices to be tested using arrays of smaller (previous generation) memory devices having the fastest timing characteristics available for those (previous generation) devices.
For example, a test system having 256 pins, testing sixteen 256 Mbit capacity memory devices, each device being organised as 16 M.times.16 bits, will require 4 Gbits (256 pins.times.16 Mb) of high speed fault capture memory to obtain single bit resolution, or if the 2 least significant address bits are ignored to obtain a 4.times.4 cell resolution, 1 Gbit of high speed memory. A 1024 pin tester would require 4 Gbit of high speed fault capture memory at the same defect resolution (a 4.times.4 cell) but this would test sixty-four 256 Mbit capacity memory devices.
This high speed fault capture memory (also called defect store memory) normally comprises Static Random Access Memory (SRAM) and can cost 30% of the total hardware cost of the test system. It is therefore highly desirable to be able to reduce the amount of fault capture memory required.
One proposed solution, which is used in some test systems, is to maintain a list of defects rather than a full map (which would indicate for each cell whether that cell is working or defective). However, this list overflows when the test system is testing a number of memory devices concurrently and one or more of those memory devices contains a large number of defects. When the list overflows, either the test sequence must be interrupted or some defect data must be discarded. Also, the controller to which the tester is attached still requires a large amount of memory, and the transfer of the data to the controller is slow.
Another prior art solution is to capture a 1:1 bitmap from the tester, requiring a large amount of storage in the tester and in a computer to which it is linked, and then to apply digital signal processing techniques to filter the data. This produces a system with negative losses, that is, it loses some of the original data, limiting its application. Even with a communication channel between the tester and computer operating at very high speed, this solution is slow because of the volume of data involved.